It has been found in fractional-n phase locked loops (PLLs) when switching from one frequency represented by n to a second frequency represented by n+1, that the phase of the output signal generated at one frequency is not always phase coherent with the same frequency signal generated at a previous time when the PLL switches back to it. What this means is that when changing from a frequency A to a frequency B and then back to a frequency A signal, the phase of the frequency A signal is not necessarily matched to that of the previously generated frequency A signal. Further, with traditional fractional-n phase locked loops the phase difference between an originally-generated frequency A signal and a subsequently-generated frequency A signal is not just a matter of a rounding error of a few degrees but may exist anywhere.
In order to preserve coherency in the fractional-n phase locked loops in the past a so-called phase resync system has been employed to preserve coherency. This phase resync system employs a periodic pulse to which the generated signals are slaved. However, these periodic pulses may introduce spurs. Moreover the pulse timing required must be precisely regulated. Otherwise the pulse timing may cause the phase locked loop to unlock if the loop bandwidth is too wide.
In fractional-n phase locked loops the switching between the n and n+1 frequencies is governed by the overflow carry bit in a traditional accumulator. This accumulator has memory in the sense that when a carry bit is generated, it is generated based on overflow from the accumulated count. Its generation is thus based on a number in the accumulator that has no necessary relationship to the timing of the carry bit used to generate an original signal. If the PLL tries to again generate a signal at this original frequency after switching to a second frequency, the carry bit used in switching back to the original frequency will not be generated at a time corresponding to the time that the carry bit for the original frequency was generated. The problem is that the phase locked loop does not start up in the same state as that of the originally-generated signal. The differing states result in different output phases and thus there is no phase coherency between the originally-generated and subsequently-generated signals of the same frequency.
It has been found that the reason lies in the way the duty cycle for n/n+1 is controlled. In the prior art duty cycle control is provided by adding a number to the accumulator used.
It is noted that the fractional-n phase locked loop is used for increased frequency resolution or fine frequency adjustment, especially in electronic warfare applications. In order to achieve fine frequency control in the fractional-n PLL, a reference frequency is first multiplied by one fractional number, n, and then by another fractional number n+1, with the fine frequency control being dependent on the duty cycle between n and n+1.
Not only is phase coherency important when utilizing a single phase locked loop, when multiple phase locked loops are utilized in a communication system it is important that all of the signals be in phase or have a predefined phase relationship between them. Because traditional fractional-n phase locked loops do not result in phase coherency, it is only with difficulty that multiple phase locked loops can be coherently phase aligned.
By way of further background, another way of preserving phase coherency in frequency generation relates to direct digital synthesis. In this regard a method is described in U.S. Pat. No. 8,115,519 to Steven E. Turner assigned to the assignee hereof and incorporated herein by reference in which phase coherency is provided by multiplying the output of a master accumulator with a frequency control word.
The result is that the sinusoidal DDS output is based on a multiple of the frequency control word and the incrementing reference phase and thus remains locked to the incrementing reference phase. This provides phase coherency even when the frequency control word changes to change the frequency.
It will be appreciated that direct digital synthesis is not generally used in battery powered radios due to its computational complexity and the resulting high power consumption. When direct digital synthesis is used in for instance battery powered units such as a handheld radio or in unmanned aerial vehicles, the power consumption of these direct digital synthesis devices can be as much as 10 times that associated with phase locked loops. The result is that direct digital synthesis is not applicable to electronic warfare systems in which power consumption and heat dissipation is a problem.
In summary, it will be appreciated that in prior fractional-n phase locked loops, the control of the switching between n/n+1 so as to adjust the duty cycle and thus the average of the two frequencies was accomplished by adding a fractional divide control number to the number in an accumulator. Since the overflow bit from the accumulator, called the carry bit, is used to control the n/n+1 switching the timing of the carry bit may be adjusted based on the fractional divide number added to the accumulator that controls when the n/n+1 switching occurs.
Since when going from frequency A to frequency B the accumulator continues to accumulate, when going back to frequency A, frequency A will start up at some undefined time depending on the accumulated count.
Note, the timing of the overflow carry bit is dependent upon the length of time that it takes to clock the accumulator from a reset point or a count of “0” to its overflow. If one wants to shorten the time period from a reset to the generation of an overflow bit one can add a fractional divide control number to the accumulator. This added number is between 1 and the number reflecting the maximum size of the accumulator, such that in the clocking of the accumulator the overflow carry bit is generated sooner than would be the case as if no number were added.
The lack of phase coherency of a frequency A signal with respect to an originally generated frequency A signal is the result of adding a number to the count in an accumulator that continues to accumulate. If this added number causes a roll over the carry bit no longer starts in phase with the carry bit used to generate the original frequency. The result is that the signal generated by the n/n+1 switching does not start in phase with the originally generated signal.
The method of adding numbers to an accumulator to control the duty cycle of the fractional-n PLL thus results in a lack of coherency between an originally generated signal and a subsequently generated signal after having switched from the original frequency to another frequency and then back again.